1. Field of the Invention
The present invention relates to a method of cleaning a substrate and cleaning recipes, and more particularly to a method of pre-cleaning a wafer and cleaning recipes used for selective epitaxial growth in a raised source/drain process to provide an epitaxial layer with a smooth surface.
2. Description of the Prior Art
Semiconductor devices are constantly being miniaturized. As the overall dimensions of semiconductor devices are made smaller and smaller, the accompanied problems such as short channel effect and junction resistance increasing are also generated. The raised source and drain has then been proposed as an alternative technique for forming a shallow junction in semiconductor devices to eliminate the aforementioned problems. Selective epitaxial growth (SEG) is the mostly used method to form the different types of eitaxy layer on semiconductor substrate, also the important process in raised source and drain technique. Because the surface of the semiconductor substrate is bombarded by ions in the previous implantation procedure, it induces the non-uniformity between two different types of epitaxial surface in the following SEG process, also affects the quality of further fabrication. How to provide a method to eliminate the quality difference in the SEG process to increase the yield of semiconductor devices that is one of the purposes of the present invention.
The cleanliness of a wafer is an important reason for the yield, properties and reliability of devices of VLSI process. More particularly, developing cleaning techniques to provide a substrate with ultra-cleanliness is quite important when the deeply sub-micron field of VLSI process is achieved. Highly pure chemical agents and DI water are used for cleaning process. Cleaning recipes of highly pure Wet Chemical Cleaning, which is developed by RCA Company in America, are used for many years. A little adjustments of the ratio of chemical recipes and cleaning sequences are developed. Reducing cleaning steps and raising cleanliness are improved, and wherein the micro-particles, oxides, mineral elements, organic and metals are the major objects to remove away.
Referring to FIG. 1, a flow chart of pre-clean steps of SEG process according to traditional cleaning steps is shown. The pre-clean steps include the following steps. In step 11, deionized (DI) water is used for fast cleaning. In step 12, a diluted hydrofluoric acid is utilized to remove the remained oxide. In step 13, deionized water is used for fast cleaning.
Referring to FIG. 2A, a MOS transistor with selective epitaxial layers formed by conventional SEG techniques is shown. The MOS transistor formed on a silicon substrate 21 comprises a polysilicon gate electrode 22, a gate oxide layer 23, an epitaxial layer 25 and a spacer 24. Before forming the epitaxial layer 25, a conventional pre-clean steps of SEG such as the one shown in FIG. 1 is utilized. In a raised source/drain process, the qualities of epitaxial layers on the P+ region and the N+ region are different. Particularly, the surface condition of the epitaxial layer on the N+ region is poor and rough. FIG. 2B shows a SEM picture of an epitaxial layer and a rough surface of the epitaxial layer on the N+ region. The roughness of the surface of the epitaxial layer would degrade the quality of following forming films thereby deteriorate the performance of devices and production yield thereof.
In view of the drawbacks mentioned with the prior art process, there is a continued need to develop new and improved processes that overcome the disadvantages associated with prior art processes. The requirements of this invention are that it solves the problems mentioned above.